1. Field of the Invention
The present invention relates to the structure of a dummy pattern in a semiconductor device. More specifically, the present invention relates to the structure of a dummy pattern in a semiconductor device in which the structure of the dummy pattern formed in a region where a metal wiring is not formed when the metal wiring is formed by means of a damascene process is improved, thus preventing generation of metal residues and a delamination phenomenon that an interlayer insulating film is fallen apart.
2. Discussion of Related Art
As a semiconductor device becomes higher integrated, the line width of a metal wiring becomes gradually narrow and the density thereof is increased. Even with a higher integration level of a device, there is a need for a rapid operating speed for the device. Accordingly, a metal wiring is formed by using a material having good electrical properties, such as copper, as a metal wiring material by means of a damascene process.
If the damascene process is performed so as to use copper as the metal wiring, a plating process and a Chemical Mechanical Polishing (CMP) process are necessarily required. In this time, if the plating process is carried out with a region where the metal wiring is not formed being left as a blanket state, a step generated between the region where the metal wiring is not formed and a region where a metal wiring is formed. Thus, after the CMP process, metal residues are created in the region where the metal wiring is not formed. In particular, if an area of the region where the metal wiring is not formed is wide and a line width of the metal wiring in the region where the metal wiring is formed is great, a more serious problem can be caused. Furthermore, if a material, which contains carbon or has a porous low dielectric constant value (low-k), is used as an interlayer insulating film, a delamination phenomenon that the interlayer insulating film is fallen apart in the region where the metal wiring is not formed is generated. Accordingly, the yield of a device is lowered. In order to solve these problems, most semiconductor manufacturers form a dummy pattern in the region where the metal wiring is not formed. However, even if the dummy pattern is formed, generation of metal residues and the delamination phenomenon of the interlayer insulating film cannot be prevented. That is, if a dummy pattern is formed without considering the structure of the dummy pattern such as a distance between the dummy patterns and the density of the dummy patterns, metal plating is thickly formed in the region where the dummy pattern is formed than in the region where the metal wiring is formed. Consequently, there is a problem in that metal residues are created after a subsequent CMP process. More particularly, if an area where a dummy pattern is formed is wide, this problem will be more severe.